SPI0 control2 register.
| SPI_MEM_CS_SETUP_TIME | (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. |
| SPI_MEM_CS_HOLD_TIME | SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. |
| SPI_MEM_ECC_CS_HOLD_TIME | SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. |
| SPI_MEM_ECC_SKIP_PAGE_CORNER | 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. |
| SPI_MEM_ECC_16TO18_BYTE_EN | Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. |
| SPI_MEM_SPLIT_TRANS_EN | Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. |
| SPI_MEM_CS_HOLD_DELAY | These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. |
| SPI_MEM_SYNC_RESET | The spi0_mst_st and spi0_slv_st will be reset. |